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Intel to integrate better security into its chips

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Jun. 18, 2010

Intel Labs is announcing two new slabs of test silicon that will further expand the company's definition of what it considers better integrated security in its various product development cycles.

Justin Rattner, director of Intel labs says "I've given our company a mandate to make security job one."

He was speaking Wednesday to reporters at the 2010 Symposium on VLSI Technology and Circuits in Honolulu, Hawaii.

"What I'm talking about is the increasing attention we're giving to security at various levels in the system," said Rattner. "How can we make our products more secure in the face of Internet attacks of all sorts — viruses, worms, rootkits and all kinds of malware — as well as making them more capable of protecting data.

One solution to that problem is in a paper that Intel is presenting at VLSI entitled "AES encryption accelerator for content protection". As Rattner explained: "One of the features in the new Westmere processor was something that we call the AES-NI, which is a group of instructions intended to accelerate AES-compatible encryption and decryption."

Overall performance enhancements from AES-NI were in the range of 3 to 10 times, but Intel customers are now asking for even more improvements to the security that is already integrated into chips and CPUs.

Intel labs has developed a 45 nm test chip that runs at 53 Gbps when performing AES encryption, a level of performance that Rattner claims is more than five times as fast as any other reported work in the field.

In addition to the encryption speed, the test chip can operate at a mere 320mV.

Although Intel may have recently proclaimed security to be job one, power savings has held that position at the chip giant for many years. Rattner made that point explicitly when he understated "I think generally that you can expect that as we report future circuit research that we'll be both pushing performance as well as striving for increased energy efficiency."

The second security-related paper that Rattner discussed was "On-chip random number generator for key generation," which supports random-number key generation in AES and other cryptographic standards.

Intel's new on-chip random-number circuitry can run at 2 Gbps, and only consumes a small 7 milli Watts of power, and is scalable down to 280 mV.

Rattner added "this is a long-debated capability. The ability to put a very high quality random-number generator in silicon chips today. And this is something we are proud of."

Rattner also claimed that Intel's new on-chip circuitry that his lab has developed has been able to pass the stringent National Institute of Standards and Technology tests for true randomness.

"The circuitry passed all tests successfully. This is not a pseudo-random generator. This is a true random-number generator," added Rattner.

However, and this is important to note, there's still a lot of debate and misconceptions about pseudo-random versus true-random, and not just at Intel but also at its largest rival, AMD.

Source: Intel.

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